> > I think maybe more important to state with all these things is that even if Phil
> gets
> > the boards it might not really be something that's easy to measure.
> >
> > People have tried to measure waitstate / DMA impact etc. with other systems and
> found
> > it to be a horribly complex subject, something that the MAME cpu cores (and general
> > architecture) isn't really up to supporting. It can be complex even for a Z80 case
> > (hence why MAME can't do ZX Spectrum properly right now) and for 68K level with DMA
> > operations from different speeds or RAM & ROM it can really become nasty to work
> out.
>
> I'm confident I can get detailed timing measurements but as you say, actually
> implementing the timing in MAME may prove challenging.
>
> Timing aside, I would otherwise be able to confirm whether or not our video emulation
> is pixel-exact under whatever cases I can test.
>
>
> > You might get a closer approximation, but I wouldn't be surprised if Phil ended up
> > with inconclusive information for some cases, as others have before him.
>
> Has anybody looked at the Cave hardware specifically? If so, I'd be curious to hear
> about their methods and results.
not the Cave hardware, I seem to recall Charles tried to measure some CPS1 stuff tho, without much success.
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