You're welcome. I'll keep hacking on the driver slowly when I've got time.
Are you in a position to dump the master clock generator PAL (82S123 32*8 BPROM at U114 on VGG board), and the colour translation PALs (82S137 1024*4 BPROMs at U10 and U11 on VGG board)? We're going to need them for proper emulation.
edit: Also need a dump of the horizontal address mapping PROM at U74 on the VGG board (appears to be 6349 512*8 with one address line tied low).