> > > I rather suspect that one of the Super Nova system's custom-named ICs is some
> sort
> > of
> > > MCU that channels the board I/O through shared RAM rather than the direct mapping
> > the
> > > driver currently provides.
> >
> > 400000-40000f looks like a somewhat usual in/ou mux to me, what makes you think
> that?
> >
> > OG.
>
> It's the analog "paddle" stuff, which is mapped to some oddly nonconsecutive bytes.
> What's even more odd about that is that the ADC on the board is a MSM6253, which has
> a microprocessor bus-compatible serial readout.
Interesting. It looks a lot like back-compatibility given the structure though.
0-3 is readonly, digital (controls, coin, test)
4-6 is readonly, three 8-bits adcs
7 is readonly, one byte of dips
As-is, you can run a complete game on that subpart. Then you have:
8 is coin lock/counter
9 is analog select between optical and voltage
10-11 is two generic, unassigned 8-bit outputs
So a 4-byte write-only block that seems a little aftertought-ish
Then:
12-13 is two generic, unassigned 8-bits input ports
14 is outputs to the interrupt controller to clear interrupts, and it's clear-on-write-0-bit to boot, which doesn't jive well with a shared/dual port ram
15 is the 4th analog input port
Frankly, that smells a lot like "ok, we forgot the coin counters, let's add them, but we have more address decoding now, what should we do with it?".
The serial aspect is interesting, but I don't see any particular problem for an asic to handle it, it's just a rotating scanning I guess.
OG.
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