When doing some study on the current non-working Daytona 2BoE, an unusual PPC CPU behavior was logged in debug mode(CROM Self Test): instead of reading ROM area, it reads an un-mapped space from 0xc3000000 to 0xc37fffff, 8 MBytes in size, exactly the same size of one ROM Bank, which is actually hard-wired at 0xff800000~0xffffffff(according to Motorola's official document of the MPC105/106 chipset).
This only happens in Daytona 2BoE, when testing the upper 16 MBytes of CROM0 and CROM1 (bank No. 2, 3, 6, and 7), and the bank number register is at 0xc3800000. It doesn't happen in Daytona 2PE, which has only 16 MBytes in each CROM group(bank 0, 1, 4, 5, 8, 9, etc).
It was first caught in MAME 0140u3, and still exist in the new released 0141u1. I also tested an earlier version in my harddisk, ver. 0135u1.
[ATTACHED IMAGE - CLICK FOR FULL SIZE]
|
Index 
Flat 
Address mapping in Model-3 PowerPC CPU board emulation?
Reply
Address mapping in Model-3 PowerPC CPU board emulation?
