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When doing some study on the current non-working Daytona 2BoE, an unusual PPC CPU behavior was logged in debug mode(CROM Self Test): instead of reading ROM area, it reads an un-mapped space from 0xc3000000 to 0xc37fffff, 8 MBytes in size, exactly the same size of one ROM Bank, which is actually hard-wired at 0xff800000~0xffffffff(according to Motorola's official document of the MPC105/106 chipset).
This only happens in Daytona 2BoE, when testing the upper 16 MBytes of CROM0 and CROM1 (bank No. 2, 3, 6, and 7), and the bank number register is at 0xc3800000. It doesn't happen in Daytona 2PE, which has only 16 MBytes in each CROM group(bank 0, 1, 4, 5, 8, 9, etc).
It was first caught in MAME 0140u3, and still exist in the new released 0141u1. I also tested an earlier version in my harddisk, ver. 0135u1.
[ATTACHED IMAGE - CLICK FOR FULL SIZE]
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Re: Address mapping error in Model-3 PowerPC CPU board emulation?
[Re: Naibo]
#244500 - 01/25/11 05:02 AM
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Ugh. So is Daytona actually using the MMU to re-map memory? That's just what I needed to hear. 
You could investigate if this is the case by dumping the PowerPC segment registers and page table.
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Bart
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| R. Belmont |
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Cuckoo for IGAvania
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Reged: 09/21/03
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Re: Address mapping error in Model-3 PowerPC CPU board emulation?
[Re: Naibo]
#244502 - 01/25/11 05:10 AM
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BTW, Scud Race in 0.141 64-bit hovers right around 100% at stock clocks on a Sandy Bridge i7-2600K. Can't wait to start overclocking... ;-)
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Re: Address mapping error in Model-3 PowerPC CPU board emulation?
[Re: R. Belmont]
#244511 - 01/25/11 05:49 AM
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Won't be long... 
My current study is based on MAME 0119, using Ville Linde's PowerPC core, which has good compatibility.
Is Ville's PPC core still availible in current version of MAME? It is quite necessary to have more than one CPU Cores co-exist, for comparing & reference. Back to 5~10 years ago, several 68000 emulators can be selected in MAME, Intepreter/DRC/C/Assemble...
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| R. Belmont |
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Cuckoo for IGAvania
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Reged: 09/21/03
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Posts: 9716
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Loc: ECV-197 The Orville
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Re: Address mapping error in Model-3 PowerPC CPU board emulation?
[Re: Naibo]
#244542 - 01/25/11 03:12 PM
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> Is Ville's PPC core still availible in current version of MAME? It is quite necessary
> to have more than one CPU Cores co-exist, for comparing & reference. Back to 5~10
> years ago, several 68000 emulators can be selected in MAME,
> Intepreter/DRC/C/Assemble...
Disagree. It is necessary to find any fix any problems with the cores that are currently in MAME. Tim S. has been doing amazing work with this on the ARM7+ core (our GBA compatibility in MESS has pretty much doubled in the last 2 weeks).
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Re: Address mapping error in Model-3 PowerPC CPU board emulation?
[Re: Naibo]
#244559 - 01/25/11 05:19 PM
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> When doing some study on the current non-working Daytona 2BoE, an unusual PPC CPU
> behavior was logged in debug mode(CROM Self Test): it reads an un-mapped space from
> 0xc3000000 to 0xc37fffff, 8 MBytes in size, exactly the same size of one ROM Bank,
> which is hard-wired at 0xff800000~0xffffffff.
Just needs the ROMs mapped there. My 603 MMU emulation is far more accurate than the previous core, and they do configure the MMU this way in daytona2. With that mapped, the self-test validates all ROMs except those that are patched.
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Hi, Aaron, :-)
I understand that your new PPC core has much advantage over the previous one.
My working on daytona2 started at once when I got the new-dumped CROMs. However, they didn't pass self-test. I've tried the newest 0141u1, earlier 0140u3, and even 0135, while the results are the same. Do I need any other modifications in model3.c?
I also tried adding the address area 0xc3000000~0xc37fffff as a mirror of rom space, the checksums changed, but still unable to pass.
[ATTACHED IMAGE]
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| R. Belmont |
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Cuckoo for IGAvania
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Re: Address mapping error in Model-3 PowerPC CPU board emulation?
[Re: Naibo]
#244567 - 01/25/11 07:00 PM
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Lemme quote Aaron's patch that passes the non-patched ROMs:
In the DRIVER_INITs for the Daytona 2 games:
memory_install_read_bank(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), 0xc3000000, 0xc37fffff, 0, 0, "bank2" );
Inside the existing CROM banking function (around line 1766 in 0.141u1):
memory_set_bankptr(space->machine, "bank2", space->machine->region( "user1" )->base() + 0x800000 + (data * 0x800000)); /* banked CROM */
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