MAMEWorld Forums - News - Vas: Let's have fun with DSPs! (QSound WIP)

The DSP16A is an interesting chip. It's like the great granddaddy of VLIW and EPIC.

The instruction set is explicitly parallel, and it can manage a 16*16->32 multiply, a 32+36->36 or 36+36->36 addition, a 12+12->12 addition, a 16+16->16 (9+9->9 on DSP16) addition, two 8-bit increments, a ROM fetch, and a RAM access in a single cycle. Yes, the word is "and", although there are limitations on the exact combinations you can use.
There are effectively no general-purpose registers - every register has an assigned role, although in some cases a few registers are interchangeable (e.g. the two accumulators and four RAM pointers).
It has dedicated silicon for saturation and rounding.
It doesn't actually have a fused multiply/add instruction (aka FMA, multiply/accumulate, MAC) - if you issue a multiply and an add in the same instruction, the add operates on the previous multiplication's product.
It has an on-board pseudorandom sequence generator.
It normally overlaps the ROM fetch for the next instruction with the current instruction, but it has a manually managed 15-instruction cache in the control unit. When executing from cache, it can overlap a ROM data fetch for the next instruction with the current instruction for higher throughput. By executing a tight loop from cache, you can make a very fast FIR filter with coefficients in ROM.
Although the DSP16 can only use internal program ROM or external program memory, but not both at the same time, the DSP16A can access external program memory while the internal ROM is enabled (QSound uses this to read sample data).
It supports multi-master time-division multiplexed synchronous serial protocols, making it ideal for processing circuit-switched voice calls in phone network switches.
The QSound DSP runs at 30MHz (60MHz clock input divided by two). On CPS2, it's already clocked at almost three times the speed of the main 68k CPU, it can issue an instruction every one or two cycles, and it can do up to four operations per instruction. The 68k main CPU takes several cycles to execute most instructions, and multiplies are particularly time-consuming. The QSound DSP is far more powerful than the main CPU - maybe 40 times the throughput.

The QSound program has been dumped for some time, and MAME has a DSP16 core. However, it doesn't implement all the functionality required to run the QSound program, and it isn't cycle-accurate, which is needed for the QSound DSP to output at a consistent sample rate. MAME's QSound device will show disassembly for the DSP program, but it won't do anything else with it. The only effects used are volume control and a simple panning table.

I've written a DSP16 core with enough functionality to run the QSound program that runs at machine cycle granularity and hooked it up in a private branch. The QSound program works, and effects are present. So what's the catch? Emulating a fast DSP costs performance - you'll need a fast computer to run it at full speed in its current form. I'm considering writing a recompiler for the DSP16 which would yield a large performance improvement.

If you want to try out the first emulator with real QSound support, the source is on github here. Be aware that it requires a fast computer to run CPS2 at full speed. It also prints some nasty validation errors, but they don't stop it from working The new QSound device source file has some notes on how it works at a high level.

I've attached a recording of the first thirty seconds of Street Fighter Zero 2 Alpha (Japan). The QSound jingle at about 8s plays all sixteen channels simultaneously with effects enabled. From about 18s you can hear the beginning of the attract loop music.